Introduction to the Chipset
The chipset is perhaps one of the most important components in any system. That's because it is the chipset that governs how all the rest of the hardware in the system interacts. It coordinates data flow of data between the system's hardware components. Not only this, but it is the chipset that defines what hardware your system can use, either by providing that hardware as part of the chipset - e.g. DMA controllers, EIDE controllers, and super-I/O controllers - or by providing support for hardware - e.g. first-party DMA (bus mastering), USB, memory and AGP (and it's various modes of operation).
The chipset also defines that type of CPU that can be used. However, this is because every chipset is actually designed around the architecture of a particular CPU or class of CPU.
The chipset provides many of the components that would previously have been present separately, such as the PCI controller, DMA controllers, IRQ controllers and EIDE controllers.
These days, choosing a chipset involves questions like:
What's the fastest processor supported by this chipset?
What's speed is the FSB?
Does this chipset support dual channel memory?
Hopefully, reading this article will help you better understand the purpose of the chipset and therefore be able to make a more informed decision, should you need to buy a new board.
Northbridge and Southbridge
If you refer back to the System Bus page, you will recall that the CPU talks memory and cache via the 'memory/system' bus and talks to I/O devices through the 'I/O bus'. These terms are obviously simplifications, but it certainly helps when trying to grasp the overall picture. The chipset must perform the integration of the various buses. In modern PCs, this is usually achieved using a two-chip architecture, where the chips are referred to as the Northbridge and the Southbridge.
Each chip in the Northbridge/Southbridge architecture has a clear set of tasks. The Northbridge coordinates high bandwidth pathways. In the diagram below, we see the CPU interfaces with the memory and AGP subsystems via the Northbridge:
Slower I/O traffic (e.g. PCI devices, EIDE, USB, Super I/O) is handled by the Southbridge.
When discussing chipset architecture, a bridge is simply an interface between different buses. In the case of the the Northbridge/Southbridge model, whether a bridge was North or South traditionally referred to the conceptual location of that portion of the chipset relative to the PCI bus (see the diagram above).
That's because the PCI bus is a Mezzanine bus, meaning that it can be used to bridge different types of bus, such as between Northbridge and Southbridge.
That's how it was, but not how it is now! A few years ago, the PCI bus provided sufficient bandwidth to permit communication between the two bridges. These days, in order to relieve the PCI bus and also to facilitate faster communication between Northbridge and Southbridge, dedicated pathways have been introduced.
Note: some texts use the term hubs rather than bridges. While these terms do smack of networking hardware, chipsets have nothing to do with networks! For example, Intel's chipsets now use what they call Intel Hub Architecture (IHA). The Northbridge has been replaced by the Graphics and Memory Controller Hub (GMCH), while the Southbridge has been replaced by the I/O Controller Hub (ICH).
Chipset example - the Via KT333
I recently sold off my old Epox 8K5A2 board which sported the VIA KT333 chipset, desigened for the AMD Athlon CPU. (Yes, I know this chipset is a bit dated, but it's a good example and the principles still apply on the more modern chipsets.)
Below is a block diagram of the KT333 chipset. From this diagram you can see that the FSB bus runs at 266MHz (using a 133MHz system clock speed). What is interesting is that the memory bus speed supports up to 333MHz (i.e. PC2700 RAM), while still running at a 266MHz FSB speed. This apparent contridiction is explained by the fact that the KT333 chipset has a '+33 modifier' option. This means that while the external CPU speed (FSB) is running at 133/266, the memory bus can run asynchronously at 333/266. Of course, this does require that you supply the correct DDR RAM.
The KT333 Northbridge controls communication between the memory bus and FSB, and is also the link to the AGP4X subsystem. The VT8235 Southbridge handles data transfers from the I/O buses, super I/O interfaces, hard disk controllers and USB 2 interfaces.
Note that North and South are linked by Via's proprietary V-Link,
which handles data flow at up to 266MB/sec. As mentioned earlier, this type of direct link
between the bridges how now replaced using the PCI bus as a Mezzanine bus.
Why? Because at only 33MHz and 32 bits wide,
the bandwidth of the PCI bus is only 127MB/sec.
Today that's barely enough for the IDE channels alone!
Today's chipsets have moved away from using the PCI bus as a bridge,
meaning that individual PCI devices get more bandwidth and also meaning that
other devices, such as IDE interfaces, don't need to share PCI bandwidth any longer.
Another example - the nVidia nForce2
Technology moves on, chips get renamed...
Chipset giants nVidia don't like the term Northbridge. They don't think it quite carries the importance of this chip. Instead, they call it either the IGP (Integrated Graphics Processor) or the SPP, depending on whether it includes integrated graphics. Clearly, the sensible choice is the SPP, since integrated graphics are usually poor performers and become rapidly outdated.
The major advantage of the nForce2 SPP is that it supports dual-channel memory. Essentially, this means that the memory controller can read from both DIMMs in a pair in parallel. This effectively doubles the bandwidth of the memory subsystem.
Other benefits include support for a 400MHz FSB (well, that's actually 200MHz), plus the AGP 8x and PCI bus run completely asynchronously, meaning that overclockers can tweak their FSB settings without worrying about the impact on other hardware.
There's nothing very special to be said about nVidia's new Southbridge, other than the fact it's not called a Southbridge. It's now called the MCP: Media and Communications Processor.
What is a bit more special is the link between the SPP and MCP. It's called the HyperTransport link and on the nForce2 currently runs at 800MB/sec.
For a power user who's considering overclocking, this type of chipset should hit the mark.
|Just Too Good
Last updated: June, 2006 (DJL)