The Data Bus and Address Bus

So far we've discussed how various buses allow data flow between components in the PC. However, one major area that I've missed is how the CPU addresses these components, i.e. how does it know what it is talking to? When it is accessing memory, how does it encode the memory address that it requires? When it is talking to hardware, how does it encode the hardware address?

Here is the final piece to the puzzle... Every bus I've described so far has really been a data bus. Every data bus also has an associated address bus and control lines. To describe how these work together, we'll use the example of fetching data from memory.

Fetching Data from Memory

Recall from the Memory section that each RAM chip has a number of address pins and a single data pin. We mentioned that to access a particular region of memory, that region, or address, must be encoded by applying voltage to a combination of these address pins.

The CPU also has a large number of pins and many of these, like in memory chips, are address pins. When the CPU needs to read a particular area of memory, the memory address that the data is stored in is encoded at the CPU's address pins. The CPU then issues a read request, causing current to flow along the set of wires connecting the CPU address pins to the memory address pins. This set of wires is collectively called the address bus. The result is that a voltage is applied to the correct pins of the memory chips.

The data to be read by the CPU then appears at the data pins of the memory chips. Recall that each memory chip has a single data pin which can either be 'on' or 'off', depending on the value of the bit read at the address specified. This signal is then sent back to the CPU along another series of wires called the data bus. The data bus connects the data pins of the memory chips to the data pins of the CPU.

The diagram below illustrates a 20 bit address bus and 8 bit data bus (as would be found in the 8088 PC) accessing a 1MB memory SIMM:

Data and address buses

When people refer to a bus, they are often referring to the data bus. The address bus is not normally discussed since it is not typically a performance influencing factor. For example, consider once again the memory address bus... In the old Intel 8088 systems, the address bus was 20 bits wide (as in the diagram above). Since 220 is 1048576, these chips could access this number of addresses (each one holding a bit value) on each chip. Recall that each address actually points to a byte of memory (see memory addressing) and that there are 8 bits to the byte. This means that these chips could access only 1048576 bytes of memory - one megabyte. The 8088 also had an 8 bit data bus, meaning that they could only fetch a single byte from memory at a time. With only one megabyte of addressable memory, the address bus was certainly a performance limiting factor.

However, in more modern processors, it is not. Consider an Intel 486 chip, which has both a 32 bit address bus and a 32 bit data bus. A 32 bit data bus means that it can fetch 4 bytes (32 bits) of data from memory at once. A 32 bit address bus can address 232 bytes - 4GB of memory. This is much more than a 486 system would ever need and explains why addressability is not typically a performance issue. Most of the Pentium family of CPUs have a 64 bit data bus and 36 bit address buses, giving access to 64Gb of memory!

There will be full details of bus widths for various chips in the Chip Guru.

Control Lines

It was mentioned earlier that each individual 'bus' is actually composed of data, address and control lines. For the sake of completeness, I'll briefly mention the control lines here.

These lines do what their name suggests. The CPU can, for example, use these lines to tell memory whether a read or a write is required. This is done by sending current down the appropriate control lines which are, not surprisingly, called the read and write lines. Similarly, a line called Memory Function Completed (MFC) is used to inform the CPU when data that has been fetched is available on the memory bus for the CPU.

IRQ lines (which will be discussed in the next section) are another example of control lines.

To see how these buses come into play when accessing other devices, look at the next section: the I/O Bus, Interrupts and DMA.