The System Bus

The term System Bus is a very ambiguous one and is perhaps one of the worst for being abused. It implies that there is a single bus connecting all peripherals. Well, in the days of the 8088 over twenty years ago this was true, from a certain point of view. (Sorry... I was having an Obi Wan moment.) However, system architectures in today's computers employ a whole suite of buses. One could define the 'System Bus' as a collective term for two lower-level buses:

(Note that each of these buses is actually a collection of buses! The memory and I/O buses are each composed of data, address and control lines. Each subset of lines can also be referred to as a bus. A discussion of the data bus, address bus and control lines will follow shortly, so I will ignore them for now.)

The memory bus connects the CPU to the memory subsystem and cache. This term 'memory bus' is often used interchangeably with 'external bus' and 'frontside bus' (more on these later). Unfortunately, many articles speak of 'the system bus' or even just 'the bus' when in fact they are refering to the memory bus (or the frontside bus). Obviously, this can lead to confusion. (I believe I may be guilty of doing this from time to time myself.)

Modern PCs make huge data demands upon the memory system. For this reason, massive bandwidth is required in the memory bus. As will be described in the CPU Guru, CPU core speeds have increased rapidly, well beyond the ability for the memory bus to keep up. This results in a major bottleneck, as the CPU 'ticks over' much more quickly than the memory bus. The result is that the CPU spends much time idle, waiting for data to delivered from the memory and cache.

In an attempt to alleviate this bottleneck, many modern systems employ what is known as the DIB (Dual Independent Bus) architecture, whereby the memory bus is split. What was previously known as the memory bus is now referred to as the frontside bus (FSB). This bus links the CPU to the chipset Northbridge, which in turn interfaces with the other subsystems, including the memory subsystem. However, an additional dedicated high-speed backside bus is also present which connects the CPU to the level 2 cache. This level 2 cache is where the CPU fetches most of its data from. The backside bus is independent of the FSB and can therefore run at much higher clockspeeds, providing much needed bandwidth to the level 2 cache. The resulting architecture can be represented as shown below:

Dual Independent Bus architecture

The I/O bus is conceptualised as 'branching off' the system bus. This bus enables devices such as hard disks, floppy drives, sound cards, modems and network cards, to talk to the CPU and to the system memory. The data demands made by such devices are much lower than the typical rates of data exchange between the CPU and the system memory. For this reason, the I/O bus delivers much lower bandwidth than the memory bus. As with the memory bus, the I/O bus is also split to give:

A component of the motherboard chipset called a bridge connects the different I/O bus types to provide a common connection to the CPU. Local I/O bus implementations (such as VESA and PCI) arrived in the early 90s to provide greater bandwidth to peripheral devices. A discussion of various I/O bus implementations can be found later in the I/O Bus Types article.

Now move on and look at the section describing the data and address buses that make up each bus...